README

Original design (http://www.sump.org/projects/analyzer)

This version SLA(0.8) was converted from VHDL to Verilog for the Altera DE2 board.

As DE2 has only 512KB SRAM (as 256K x 16bit), only 16 channels are supported. 
(But I kept the coding as 32 channels)

I found that sometimes the device stuck at the Finite State Machine in receiver module (I don't know
if it is the same in the original Xilinx board). Reset key is KEY3 on DE2 board. I modified the module 
receiver.v a bit to slow down the clock (from 100M to trxClock), the situation improved a bit.

During compilation, there may be a Critical Warning that the timing requirements could not be met. 
I found that it is due to the external clock input, so it does not affect the function of the circuit.

For floating input channels, there will be noise shown. Ground them if you care.

Please let me know if you have any special findings (ktsang@bcs.org.uk)